RISC-V: Новая архитектура и экосистема для будущего вычислительных систем

RISC-V AND THE BIRTH OF THE NEW COMPUTER ARCHITECTURE ECOSYSTEM

It is not often you get to watch the birth of a new computer architecture ecosystem unfold. Announced in 2010, RISC-V has recently seend an increase in momentum as measured in the
public development activity of software required to make RISC-V useful. This may seem like an odd way to measure momentum (sorry physicists!), but these are necessary steps for wider adoption of the new open instruction set architecture. As these tools mature they will form the basis for enabling more exotic variants and implementations of the RISC-V architecture. Note that there is already shipping RISC-V hardware in the form of a development kit from Suffice.

Hardware Enablement: Software Makes Hardware Useful

New hardware doesn’t do anything without software. The shortest path to making a new architecture useful is not to write new assemblers, compilers and related software tools but instead extend existing software tools like bimetals and gecko so that they support the new architecture. Extending these tools to support a new architecture is called d adding a backend port.

RISC-V Hello World and Instruction Trace

To add new hardware support to an existing toolchain or operating system simply pick a recent snapshot of the codebase, make a local development copy, make the required changes, and release a toolchain and OS. If you would like to follow along with the early RISC-V software you can see the work in progress here in the RISC-V get repos.

Upstreaming in Open Source: Reducing the Maintenance Burden

As the RISC-V software tools mature and stabilize, they are very likely to be submitted upstream so they become part of the mainline development for that particular tool or OS. Upstream acceptance is important because maintaining these codebases out-of-tree is more work than maintaining the codebase upstream.

The upstream public codebase changes over time and new releases are made. The out-of-tree tools team is then forced to bring all of the new public codebase changes into the out-of-tree codebase to keep the tool current with bug fixes and other desirable changes. Over time, this can get very hard or even impossible if the interfaces change or go away.

If instead your changes are accepted upstream, maintenance is now everyone’s responsibility: Proposed changes to that codebase must go through code review and testing to make sure that they do not break things. Not only is this less work overall, ideally the maintenance workload is distributed on all the volunteers maintaining the project, not just the team responsible for your part of it.

Other open source tool and OS efforts have failed to get their changes accepted upstream because, while the work required is highly technical, it also involves understanding how to work with the existing codebase and the existing development community. Essentially you want to understand and adhere to the existing norms of the project’s development community and make your case that your implementation is also technically sound. To paraphrase an old friend, you want to make it easy for the existing project maintainers to give you an “A” and accept your proposed changes.

Recent RISC-V Open Source Toolchain Progress

It appears that the RISC-V team has been working well with the existing bimetals, gecko and gab communities. Here is a sample of some of the upstream proposals, patch submissions, discussions, commits and releases since the end of 2016 into mid-2017:

bimetals (assembler, linker and related tools)

Committed upstream on November 1, 2016. Bimetals version 2.28 released on March 3, 2017 and included RISC-V support:

binutils commit message

RISC-V saw-dev ml bimetals release announcement

gecko (compiler for C and other languages)

Patch submission on January 11, 2017. Changes committed upstream on February 2, 2017. GCC version 7.1 released on May 2, 2017 and included RISC-V support.

GCC port submitted upstream

GCC port accepted

GCC port commit message

SiFive GCC upstream blog post

GCC 7 changes includes RISC-V support

Other RISC-V Related Works in Progress

Here are some ongoing RISC-V tool and OS projects and some upstream discussions in those communities.

Linux kernel (step 1 in Linux OS support) Get repo, Thread from May 22, 2017.

glib (The GNU C Library, step 2 in Linux OS support. Enables many already written C language Linux user space programs): Get, Thread from June 14, 2017.

LLVM (another compiler toolchain comparable to GCC): Get repo, Thread from August 17, 2016.

GDB (debugger for the GCC toolchain): Get repo.

QEMU (hardware emulator so you can run software without the targeted hardware): Get repo.

Side Note: Does RISC-V refer to a single instruction set architecture?

No. I’ll quote RISC-V software developer Palmer Dab belt who wrote the following in a recent mailing list posting:

RISC-V is a modular ISA, and as such there are many ISA variants. The

actual number is the Cartesian product of:

* RV32I, RV64I: base ISA, which defines the length of GP registers

(which we call XLEN).

* M or no-M: multiply support or not.

* A or no-A: atomic instruction support or not.

* none, F, or D: the floating-point format supported, either none,

single or double.

* C or no-C: compressed instructions support or not.

In addition to the ISA variants, we support soft, single-hard, and

double-hard float ABIs on any ISA that includes the required

floating-point registers.

At the risk of embarrassing myself with simple math mistakes:

2 x 2 x 2 x 1 x 2 or 16 ISA variants without floating point support and

2 x 2 x 2 x 2 x 2 or 32 ISA variants with floating point support.

That’s 48 ISA variants.

How many combinations of ISA variants and FP-ABI options are there?

All 48 of those ISA variants support the soft-FP ABI where the hardware performs floating point operations whether or not it has the FP registers and floating point hardware support to make those operations fast.

Only 16 of the FP ISA variants support the single-hard float ABI.

Only 16 of the FP ISA variants support the double-hard float ABI.

That’s 48 soft-FP + 16 single-hard + 16 double-hard equals 80 valid RISC-V ISA/FP-ABI combinations.

Адрес публикации: https://www.prodlenka.org/metodicheskie-razrabotki/324416-risc-v-and-the-birth-of-the-new-computer-arch